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oxford semiconductor ltd. 25 milton park, abingdon, oxon, ox14 4sh, uk tel: +44 (0)1235 824900 fax: +44(0)1235 821141 oxford semiconductor 1999 OX12PCI840 1.2 ? dec 2001 part no. OX12PCI840 - p qc - a f eature ieee1284 spp/epp/ecp parallel port single function target pci controller, fully pci 2.2 and pci power management 1.0 compliant 2 multi - purpose io pins which can be configured as interrupt input pins can be reconfigured using optional non - vo latile configuration memory (eeprom) 5.0v operation 100 pin pqfp package d escription the OX12PCI840 is a single chip solution for pci - based parallel expansion add - in cards. it is a single function pci device. for legacy applications the pci resources a re arranged so that the parallel port can be located at standard i/o addresses. the efficient 32 - bit, 33mhz target - only pci interface is compliant with version 2.2 of the pci bus specification and version 1.0 of pci power management specification. for ful l flexibility, all the default register values can be overwritten using an optional microwire tm serial eeprom. the OX12PCI840 provides an ieee1284 epp/ecp parallel port which fully supports the existing centronics interface. OX12PCI840 integrated parallel port and pci interface
data sheet revision 1.2 page 2 OX12PCI840 oxford semiconductor ltd. c ontents 1 pin information ................................ ................................ ................................ ..................... 4 2 pin descriptions ................................ ................................ ................................ .................... 5 3 configuration & oper ation ................................ ................................ ............................... 8 4 pci target controlle r ................................ ................................ ................................ ....... 9 4.1 operation ................................ ................................ ................................ ................................ ................................ .......... 9 4.2 configuration space ................................ ................................ ................................ ................................ ................... 9 4.2.1 pci configuration sp ace register map ................................ ................................ ................................ ......... 10 4.3 accessing logical fu nctions ................................ ................................ ................................ ................................ 11 4.3.1 pci access to parall el port ................................ ................................ ................................ .............................. 11 4.4 accessing local conf iguration registers ................................ ................................ ................................ .... 12 4.4.1 local configuration and control reg ister ?lcc? (offset 0x00) ................................ ......................... 12 4.4.2 multi - purpose i/o co nfiguration register ?mic? (offset 0x04) ................................ ............................. 13 4.4.3 local bus timing par ame ter register 1 ?lt1? (offset 0x08): ................................ ................................ ... 13 4.4.4 local bus timing par ameter/bar sizing re gister 2 ?lt2? (offs et 0x0c): ................................ ............. 14 4.4.5 glob al interrupt status and control register ?gis? (offset 0x10 ) ................................ ................. 15 4.5 pci interrupts ................................ ................................ ................................ ................................ ............................... 16 4.6 power management ................................ ................................ ................................ ................................ .................... 17 4.6.1 power management usi ng mio ................................ ................................ ................................ ............................ 17 5 bi - directional paral lel port ................................ ................................ .......................... 18 5.1 operati on and mode selectio n ................................ ................................ ................................ ............................. 18 5.1.1 spp mode ................................ ................................ ................................ ................................ ................................ ...... 18 5.1.2 ps2 mode ................................ ................................ ................................ ................................ ................................ ...... 18 5.1 .3 epp mode ................................ ................................ ................................ ................................ ................................ ...... 18 5.1.4 ecp mode ................................ ................................ ................................ ................................ ................................ ...... 18 5.2 parallel port interr upt ................................ ................................ ................................ ................................ ......... 18 5.3 register description ................................ ................................ ................................ ................................ ................. 19 5.3.1 parallel port data r egister ?pdr? ................................ ................................ ................................ ................... 19 5.3.2 ecp fifo address / r le ................................ ................................ ................................ ................................ ........... 19 5.3.3 device status regist er ?dsr? ................................ ................................ ................................ .............................. 19 5.3.4 device control regis ter ?dcr? ................................ ................................ ................................ .......................... 20 5.3.5 epp ad dress register ?eppa ? ................................ ................................ ................................ ............................... 20 5.3.6 epp data registers ? eppd1 - 4? ................................ ................................ ................................ ............................... 20 5.3.7 ecp data fifo ................................ ................................ ................................ ................................ ............................. 20 5.3.8 test fifo ................................ ................................ ................................ ................................ ................................ ...... 20 5.3.9 configuration a regi ster ................................ ................................ ................................ ................................ ... 20 5.3.10 configuration b regi ster ................................ ................................ ................................ ................................ ... 21 5.3.11 extended control reg ister ?ecr? ................................ ................................ ................................ .................... 21 6 serial eeprom ................................ ................................ ................................ ...................... 22 6.1 specification ................................ ................................ ................................ ................................ ................................ . 22 6.2 eeprom data organisa tion ................................ ................................ ................................ ................................ ..... 22 6.2.1 zone0: header ................................ ................................ ................................ ................................ ............................ 22 6.2.2 zon e1: local configurat ion registers ................................ ................................ ................................ ......... 23 6.2.3 zone2: identificatio n registers ................................ ................................ ................................ ........................ 23 6.2.4 zone3: pci configura tion registers ................................ ................................ ................................ ............... 23 6.2.5 zone4: function acce ss ................................ ................................ ................................ ................................ ........ 25 7 operating conditions ................................ ................................ ................................ ........ 26
data sheet revision 1.2 page 3 OX12PCI840 oxford semiconductor ltd. 8 dc elect rical characteristic s ................................ ................................ ...................... 26 8.1 non - pci i/o buffers ................................ ................................ ................................ ................................ ...................... 26 8.2 pci i/o buffers ................................ ................................ ................................ ................................ ............................... 27 9 ac electrical charac teristics ................................ ................................ ...................... 28 9.1 pci bus ................................ ................................ ................................ ................................ ................................ ............... 28 10 timing waveforms ................................ ................................ ................................ ............ 29 11 package details ................................ ................................ ................................ .............. 30 12 notes ................................ ................................ ................................ ................................ .. 31 13 contact details ................................ ................................ ................................ ............... 32
data sheet revision 1.2 page 4 OX12PCI840 oxford semiconductor ltd. 1 p in i nform ation 100 pin qfp ee_di ee_do ee_cs test stb afd# init# slin# gnd ac ack# nc pd_en err# vdd dc gnd dc slct busy pe pd0 gnd ac pd1 pd2 pd3 pd4 vdd ac gnd ac pd5 pd6 pd7 mio0 80 75 70 65 60 55 51 ee_sk 81 50 ad0 mio1 ad1 z_inta gnd ac z_reset ad2 gnd dc 85 ad3 pci_clk 45 vdd dc vdd dc gnd dc z_pme ad4 ad31 ad5 ad30 90 gnd ac ad29 40 vdd ac gnd ac ad6 ad28 ad7 ad27 z_cbe0 ad26 95 ad8 gnd ac 35 gnd ac vdd ac ad9 ad25 ad10 ad24 ad11 z_cbe3 100 31 ad12 1 5 10 15 20 25 30 idsel ad23 gnd ac ad22 ad21 ad20 gnd ac vdd ac ad19 ad18 ad17 ad16 z_cbe2 z_frame gnd dc vdd dc z_irdy z_trdy z_devsel gnd ac z_stop z_perr z_serr par z_cbe1 ad15 ad14 ad13 gnd ac vdd ac
data sheet revision 1.2 page 5 OX12PCI840 oxford semiconductor ltd. 2 p in d escriptions pin numbers dir 1 name description pci interface 89,90,91,93,94,95,98,99,2,4,5,6,9, 10,11,12,26,27,28,31,32,33,34,36, 38,39,42,43,46,47,49,50 p_i/o ad[31:0] multiplexed pci address/data bus 100,13,25,37 p_i c/be[3:0]# pci comm and/byte enable 86 p_i clk pci system clock 14 p_i frame# cycle frame 19 p_o devsel# device select 17 p_i irdy# initiator ready 18 p_o trdy# target ready 21 p_o stop# target stop request 24 p_i/o par parity 23 p_o serr# system error 22 p_i/o perr# parity error 1 p_i idsel initialisation device select 84 p_i rst# pci system reset 83 p_od inta# pci interrupt 88 p_od pme# power management event
data sheet revision 1.2 page 6 OX12PCI840 oxford semiconductor ltd. pin numbers dir 1 name description parallel port 71 i i ack# intr# acknowledge (spp mode). ac k# is asserted (low) by the peripheral to indicate that a successful data transfer has taken place. identical function to ack# (epp mode). 63 i pe paper empty. activated by printer when it runs out of paper. 64 i i busy wait# busy (spp mode). busy i s asserted (high) by the peripheral when it is not ready to accept data wait (epp mode). handshake signal for interlocked ieee 1284 compliant epp cycles. 73 od o slin# addrstb# select (spp mode). asserted by host to select the peripheral address stro be (epp mode) provides address read and write strobe 65 i slct peripheral selected. asserted by peripheral when selected. 68 i err# error. held low by the peripheral during an error condition. 74 od o init# init# initialise (spp mode). commands the pe ripheral to initialise. initialise (epp mode). identical function to spp mode. 75 od o afd# datastb# auto feed (spp mode, open - drain) data strobe (epp mode) provides data read and write strobe 76 od o stb# write# strobe (spp mode). used by periph eral to latch data currently available on pd[7:0] write (epp mode). indicates a write cycle when low and a read cycle when high 52,53,54,57, 58,59,60,62 i/o pd[7:0] parallel data bus
data sheet revision 1.2 page 7 OX12PCI840 oxford semiconductor ltd. pin numbers dir 1 name description multi - purpose & external inter rupt pins 82, 51 i/o mio[1:0] multi - purpose i/o pins. can drive high or low, or assert a pci interrupt eeprom pins 81 o ee_ck eeprom clock 78 o ee_cs eeprom active - high chip select 80 iu ee_di eeprom data in. when the serial eeprom is connected, this pin should be pulled up using 1 - 10k resistor. when the eeprom is not used the internal pull - up is sufficient. 79 o ee_do eeprom data out. miscellaneous pins 77 i test test pin : should be held low at all times power and ground 2 8,30,40,56,97 v ac vd d supplies power to output buffers in switching (ac) state 16,45,67,87 v dc vdd power supply. supplies power to core logic, input buffers and output buffers in steady state 3,7,20,29,35,41,48,55,61,72,92,96 g ac gnd supplies gnd to output buffers in switching (ac) state 15,44,66,85 g dc gnd ground (0 volts). supplies gnd to core logic, input buffers and output buffers in steady state table 1 : pin descriptions note 1: direction key: i input id input with internal p ull - down o output i/o bi - directional od open drain nc no connect z high impedance p_i pci input p_o pci output p_i/o pci bi - directional p_od pci open drain g ground v 5.0v power note 2: power & ground there are two gnd and two vdd rails internally. one set of rails supply power and ground to output buffers while in switching state (called ac power) and another rail supply the core logic, input buffers and output buffers in steady - state (called dc rail). the rails are not connected internally. this precau tion reduces the effects of simultaneous switching outputs and undesirable rf radiation from the chip. further precaution is taken by segmenting the gnd and vdd ac rails to isolate the pci and local bus pins.
data sheet revision 1.2 page 8 OX12PCI840 oxford semiconductor ltd. 3 c onfiguration & o peration the OX12PCI840 is a single function, target - only pci device, compliant with the pci local bus specification, revision 2.2 and pci power management specification, revision 1.0. the OX12PCI840 is configured by system start - up software during the bootstrap process that follo ws bus reset. the system scans the bus and reads the vendor and device identification codes from any devices it finds. it then loads device - driver software according to this information and configures the i/o, memory and interrupt resources. device drivers can then access the functions at the assigned addresses in the usual fashion, with the improved data throughput provided by pci. there are a set of local configuration registers that can be used to enable signals and interrupts, and configure timings. t hese can be set up by drivers or from the eeprom. all registers default after reset to suitable values for typical applications. however, all identification, control and timing registers can be redefined using an optional serial eeprom. as an additional e nhancement, the eeprom can be used to program the parallel port, allowing pre - configuration, without requiring driver changes.
data sheet revision 1.2 page 9 OX12PCI840 oxford semiconductor ltd. 4 pci t arget c ontroller 4.1 operation the OX12PCI840 responds to the following pci transactions: - configuration access: the ox12p ci840 responds to type 0 configuration reads and writes if the idsel signal is asserted and the bus address is selecting the configuration registers for function 0. the device will respond to the configuration transaction by asserting devsel#. data transfe r then follows. any other configuration transaction will be ignored by the OX12PCI840. io reads/writes: the address is compared with the addresses reserved in the i/o base address registers (bars). if the address falls within one of the assigned ranges, the device will respond to the io transaction by asserting devsel#. data transfer follows this address phase. only byte accesses are possible to the function bars (excluding the local configuration registers for which word, dword access is supported). for io accesses to these regions, the controller compares ad[1:0] with the byte - enable signals as defined in the pci specification. the access is always completed; however if the correct be signal is not present the transaction will have no effect. memory rea ds/writes: these are treated in the same way as i/o transactions, except that the memory ranges are used. memory access to single - byte regions is always expanded to dwords in the OX12PCI840. in other words, OX12PCI840 reserves a dword per byte in single - by te regions. the device allows the user to define the active byte lane using lcc[4:3] so that in big - endian systems the hardware can swap the byte lane automatically. for memory mapped access in single - byte regions, the OX12PCI840 compares the asserted byte - enable with the selected byte - lane in lcc[4:3] and completes the operation if a match occurs, otherwise the access will complete normally on the pci bus, but it will have no effect on either the parallel port or the local bus controller. all other cycles (64 - bit, special cycles, reserved encoding etc.) are ignored. the OX12PCI840 will complete all transactions as disconnect - with - data, i.e. the device will assert the stop# signal alongside trdy#, to ensure that the bus master does not continue with a burs t access. the exception to this is retry, which will be signalled in response to any access while the OX12PCI840 is reading from the serial eeprom. the OX12PCI840 performs medium - speed address decoding as defined by the pci specification. it asserts the devsel# bus signal two clocks after frame# is first sampled low on all bus transaction frames which address the chip. fast back - to - back transactions are supported by the OX12PCI840 as a target, so a bus master can perform faster sequences of write transact ions to the parallel port when an inter - frame turn - around cycle is not required. the device supports any combination of byte - enables to the pci configuration registers and the local configuration registers (see base address 2 and 3). if a byte - enable is n ot asserted, that byte is unaffected by a write operation and undefined data is returned upon a read. the OX12PCI840 performs parity generation and checking on all pci bus transactions as defined by the standard. if a parity error occurs during the pci b us address phase, the device will report the error in the standard way by asserting the serr# bus signal. however if that address/command combination is decoded as a valid access, it will still complete the transaction as though the parity check was correc t. the OX12PCI840 does not support any kind of caching or data buffering, other than that in the parallel port interface itself. 4.2 configuration space the OX12PCI840 is a single function device, with one configuration space. all required fields in the stan dard header are implemented, plus the power management extended capability register set. the format of the configuration space is shown in table 2 overleaf. in general, writes to any registers that are not implemented are ignored , and all reads from unimplemented registers return 0.
data sheet revision 1.2 page 10 OX12PCI840 oxford semiconductor ltd. 4.2.1 pci configuration space register map configuration register description offset 31 16 15 0 address device id vendor id 00h status command 04h class code revision id 08h bist 1 header type rese rved reserved 0ch base address register 0 (bar0) - function in i/o space 10h base address register 1 (bar 1) - function in i/o space 14h base address register 2 (bar 2) ? local configuration registers in io space 18h base address register 3 (bar3) ? l ocal configuration registers in memory space 1ch base address register 4 (bar4) ? function in memory space 20h reserved 24h reserved 28h subsystem id subsystem vendor id 2ch reserved 30h reserved cap_ptr 34h reserved 38h reserved reserved interrupt pin interrupt line 3ch power management capabilities (pmc) next ptr cap_id 40h reserved reserved pmc control/status register (pmcsr) 44h table 2 : pci configuration space program read/write register name reset value eeprom p ci vendor id 0x1415 w r device id 0x8403 w r command 0x0000 - r/w status 0x0290 w(bit 4) r/w revision id 0x00 - r class code 0x070103 w r header type 0x00 - r bar 0 0x00000001 - r/w bar 1 0x00000001 - r/w bar 2 0x00000001 - r/w bar 3 0x00000000 - r/w bar 4 reserved - r/w subsystem vid 0x1415 w r subsystem id 0x0001 w r cap ptr. 0x40 - r interrupt line 0x00 - r/w interrupt pin 0x01 w r cap id 0x01 - r next ptr. 0x00 - r pm capabilities 0x6c01 w r pmc control/ status register 0x0000 - r/w table 3 : pci configuration space default values
data sheet revision 1.2 page 11 OX12PCI840 oxford semiconductor ltd. 4.3 accessing logical functions access to the parallel port is achieved via standard i/o and memory mapping, at addresses defined by the base address registers (bars) in configuration space. the bars are configured by the system to allocate blocks of i/o and memory space to the logical function, according to the size required by the function. the addresses allocated can then be used to access the function. the mapping of these bars is shown in table 4 . bar mapping 0 parallel port base registers (i/o mapped) 1 parallel port extended registers (i/o mapped) 2 local configuration registers (i/o mapped 3 local configuration registers (memory mapped) 4 unused 5 unused table 4 : base address register definition 4.3.1 pci access to parallel port access to the port works with two i/o bars corresponding to the two sets of registers defined to operate an ieee1284 ecp/epp and bi - directional paral lel port. the user can change the i/o space block size of bar0 or bar by over - writing the default values using the serial eeprom (see section 4.4 ). legacy parallel ports expect the upper register set to be mapped 0x400 above the base block, therefore if the bars are fixed with this relationship, generic parallel port drivers can be used to operate the device in all modes. example: bar0 = 0x00000379 (8 bytes at address 0x378) bar1 = 0x00000779 (8 bytes at address 0x778) if th is relationship is not used, custom drivers will be needed.
data sheet revision 1.2 page 12 OX12PCI840 oxford semiconductor ltd. 4.4 accessing local configuration registers the local configuration registers are a set of device specific registers which can always be accessed. they are mapped to the i/o and memory addresses set up in bar2 and bar3, with the offsets defined for each register. i/o or memory accesses can be byte, word or dword accessed, however on little - endian systems such as intel 80x86 the byte order will be reversed. 4.4.1 local configuration and control register ?lcc? (offset 0x00) this register defines control of ancillary functions such as power management, endian selection and the serial eeprom. the individual bits are described below. bits description read/write reset eeprom pci 2:0 reserved 000 4:3 endian byte - lane select for memory access to parallel port 00 = select data[7:0] 10 = select data[23:16] 01 = select data[15:8] 11 = select data[31:24] memory access to OX12PCI840 is always dword aligned. when accessing the parallel port, this option selects the active byte lane. as both pci and pc architectures are little endian, the default value will be used by systems, however, some non - pc architectures may need to select the byte lane. w rw 00 7:5 power - down filter time. these bits define a value of an internal filter time for power - down interrupt request in power management circuitry in function0. once function0 is ready to go into power down mode, OX12PCI840 will wait for the specified filte r time and if function0 is still in power - down request mode, it can assert a pci interrupt (see section 4.6 ). w rw 000 000 = power - down request disabled 001 = 4 seconds 010 = 129 seconds 011 = 518 seconds 1xx = immediate 10:8 reserved: power management test bits. the device driver must write zero to these bits - r 000 22:11 reserved. - r 0000h 23 parallel port input (glitch) filters. enabled when ?1? w rw 0 24 eeprom clock. for pci read or write to the eeprom , toggle this bit to generate an eeprom clock (ee_ck pin). - rw 0 25 eeprom chip select. when 1 the eeprom chip - select pin ee_cs is activated (high). when 0 ee_cs is de - active (low). - rw 0 26 eeprom data out. for writes to the eeprom, this output bit is the inp ut - data of the eeprom. this bit is output on ee_do and clocked into the eeprom by ee_ck. - rw 0 27 eeprom data in. for reads from the eeprom, this input bit is the output - data of the eeprom connected to ee_di pin. - r x 28 eeprom valid. a 1 indicates tha t a valid eeprom program is present - r x 29 reload configuration from eeprom. writing a 1 to this bit re - loads the configuration from eeprom. this bit is self - clearing after eeprom read - rw 0 30 reserved - r 0 31 reserved - r 0
data sheet revision 1.2 page 13 OX12PCI840 oxford semiconductor ltd. 4.4.2 multi - purpos e i/o configuration register ?mic? (offset 0x04) this register configures the operation of the multi - purpose i/o pins ?mio[1:0] as follows. bits description read/write reset eeprom pci 1:0 mio0 configuration register 00 - > mio0 is a non - inverting i nput pin 01 - > mio0 is an inverting input pin 10 - > mio0 is an output pin driving ?0? 11 - > mio0 is an output pin driving ?1? w rw 00 3:2 mio1 configuration register 00 - > mio1 is a non - inverting input pin 01 - > mio1 is an inverting input pin 10 - > m io1 is an output pin driving ?0? 11 - > mio1 is an output pin driving ?1? w rw 00 4 mio0_pme enable. a value of ?1? enables mio0 pin to set the pme_status in pmcsr register, and hence assert the pme# pin if enabled. a value of ?0? disables mio0 from setti ng the pme_status bit. w rw 0 5 mio1_pme enable. a value of ?1? enables mio1 pin to set the pme_status in pmcsr register, and hence assert the pme# pin if enabled. a value of ?0? disables mio1 from setting the pme_status bit. w rw 0 6 mio0 power down req uest: a ?1? enables mio0 to control the power down request filter. w rw 0 7 mio1 power down request: a ?1? enables mio1 to control the power down request filter. w rw 0 31:8 reserved - r 00 4.4.3 local bus timing parameter register 1 ?lt1? (offset 0x08): t he local bus timing parameter registers (lt1 and lt2) define the operation and timing parameters used by the internal local bus (that connects to the parallel port). it is envisaged that these should not need to be changed by the user . the timing parameter s are programmed in 4 - bit registers to define the assertion/de - assertion of the local bus control signals. the values programmed in these registers defines the number of pci clock cycles after a reference cycle when the events occur, where the reference cy cle is defined as two clock cycles after the master asserts the irdy# signal. the timings refer to i/o or memory mapped accesses. bits description read/write reset eeprom pci 3:0 read cycle start w rw 0h 7:4 read cycle end w rw 2h 11:8 write cycle start w rw 0h 15:12 write cycle end w rw 2h 19:16 read assertion w rw 1h 23:20 read de - assertion w rw 2h 27:24 write assertion w rw 1h 31:28 write de - assertion w rw 2h note 1: only values in the range of 0h to ah (0 - 10 decimal) are valid. othe r values are reserved. see notes in the following page.
data sheet revision 1.2 page 14 OX12PCI840 oxford semiconductor ltd. 4.4.4 local bus timing parameter/bar sizing register 2 ?lt2? (offset 0x0c): bits description read/write reset eeprom pci 3:0 reserved: 0h must be written to this location w rw 0h 7:4 reserved: fh must be written to this location w rw fh 11:8 reserved: 2h must be written to this location w rw 2h 15:12 reserved: 0h must be written to this location w rw 0h 19:16 reserved. - r 0h 22:20 io space block size of bar0 w r 000 = reserved 001 = 4 bytes 010 = 8 bytes 011 = 16 bytes 100 = 32 bytes 101 = 64 bytes 110 = 128 bytes 111 = 256 bytes ?010? 23 reserved - r 0h 26:24 io space block size of bar1 w r 000 = reserved 001 = 4 bytes 010 = 8 bytes 011 = 16 bytes 100 = 32 bytes 101 = 64 byte s 110 = 128 bytes 111 = 256 bytes ?001? 28::27 reserved - r 000 29 reserved:0 must be written to this location - rw 0 31:30 reserved:00 must be written to this location w rw 00
data sheet revision 1.2 page 15 OX12PCI840 oxford semiconductor ltd. 4.4.5 global interrupt status and control register ?gis? (offset 0x10) bits desc ription read/write reset eeprom pci 1:0 reserved - r 0x0h 2 mio0 this bit reflects the state of the internal mio[0]. the internal mio[0] reflects the non - inverted or inverted state of mio0 pin. - r x 3 mio1 this bit reflects the state of the int ernal mio[0]. the internal mio[0] reflects the non - inverted or inverted state of mio0 pin. - r x 17 - 4 reserved - r 0 18 mio0 inta enable when set (1) allows mio0 to assert a pci interrupt on the inta line. state of mio0 that causes an interrupt is de pendant upon the polarity set by mic(1:0) w rw 0 19 mio1 inta enable when set (1) allows mio1 to assert a pci interrupt on the inta line. state of mio1 that causes an interrupt is dependant upon the polarity set by mic(3:2) w rw 0 20 power - down inter rupt this is a sticky bit. when set, it indicates a power - down request issued and would normally have asserted a pci interrupt if bit 21 was set (see section 7.9). reading this bit clears it. - r x 21 power - down interrupt enable. when ?1? a power down request is allowed to generate an interrupt. w rw 0 22 parallel port interrupt status - r 0 23 parallel port interrupt enable w rw 1 31:24 reserved - r 000h
data sheet revision 1.2 page 16 OX12PCI840 oxford semiconductor ltd. 4.5 pci interrupts interrupts in pci systems are level - sensitive and can be shared. there are three sources of interrupt in the OX12PCI840, two from multi - purpose io pins (mio1 to mio0) and one from the parallel port. all interrupts are routed to the pci interrupt pin inta#. the default routing asserts function0 interrupts on inta#. this default routing may be modified (to disable interrupts) by writing to the interrupt pin field in the configuration registers using the serial eeprom facility. the interrupt pin field is normally considered a hard - wired read - only value in pci. it indicates to syst em software which pci interrupt pin (if any) is used by a function. the interrupt pin may only be modified using the serial eeprom facility, and card developers must not set any value which violates the pci specification. note that OX12PCI840 only has one pci interrupt pin - inta#. if in doubt, the default routings should be used. table 5 relates the interrupt pin field to the device pin used. interrupt pin device pin used 0 none 1 inta# 2 to 255 reserved table 5 : ?interrupt pin? definition during the system initialisation process and pci device configuration, system - specific software reads the interrupt pin field to determine which (if any) interrupt pin is used by the function. it programme s the system interrupt router to logically connect this pci interrupt pin to a system - specific interrupt vector (irq). it then writes this routing information to the interrupt line field in the function?s pci configuration space. device driver software mus t then hook the interrupt using the information in the interrupt line field. interrupt status for all sources of interrupt is available using the gis register in the local configuration register set, which can be accessed using i/o or memory accesses. all interrupts can be enabled / disabled individually using the gis register set in the local configuration registers. when an mio pin is enabled, an external device can assert a pci interrupt by driving that pin. the sense of the mio external interrupt pi ns (active - high or active - low) is defined in the mic register. the parallel port can also assert an interrupt.
data sheet revision 1.2 page 17 OX12PCI840 oxford semiconductor ltd. 4.6 power management the OX12PCI840 is compliant with pci power management specification revision 1.0. the function implements its own set of powe r management registers and supports the power states d0, d2 and d3. power management is accomplished by power - down and power - up requests, asserted via interrupts and the pme# pin respectively. the pme# pin is de - asserted when the sticky pme_status bit is c leared. power - down request is not defined by power management 1.0. it is a device - specific feature and requires a bespoke device driver implementation. the device driver can either implement the power - down itself or use a special interrupt and power - down features offered by the device to determine when the device is ready for power - down. the pme# pin can, in certain cases, activate the pme# signal when power is removed from the device, which will cause the pc to wake up from low - power state d3(cold). to ensure full cross - compatibility with system board implementations, use of an isolator fet is recommended. if power management capabilities are not required, the pme# pin can be treated as no - connect. 4.6.1 power management using mio the power - down request for the parallel port is application - dependent. provided that the necessary enables have been set in the local registers, the multi - purpose i/o pins mio(1:0) can be used to generate a powerdown request. the mio state that governs powerdown is the inverse of t he mio state that asserts the inta line (if that option were to be enabled). this means that when the external device is not interrupting it will begin the powerdown cycle. for greater flexibility in the generation of the power down request,, a powerdown f ilter is also available to ensure that the relevant mio pins remain stable for a selectable period before a powerdown request is issued. function0 implements the pci power management power - states d0, d2 and d3. whenever the device driver changes the powe r - state to state d2 or d3, function0 takes the following actions: - the pci interrupt for function0 is disabled. access to i/o or memory bars of function0 is disabled. however, access to the configuration space is still enabled. the device driver can optio nally assert/de - assert any of its selected (design dependent) mio pins to switch off vcc, disable other external clocks, or activate shut - down modes to any external devices. function0 can issue a wake up request by using the mio pins. when mic[7] or mic[6 ] is set, rising or falling edge of the relevant mio pin will cause function0 to issue a wake up request by setting pme_status = (pmcsr[15]), if it is enabled by pmcsr[8] of function0. pme_status is a sticky bit which will be cleared by writing a ?1? to i t. after a wake up event is signalled, the device driver is expected to return the function to the d0 power - state.
data sheet revision 1.2 page 18 OX12PCI840 oxford semiconductor ltd. 5 b i - directional p arallel p ort 5.1 operation and mode selection the OX12PCI840 offers a compact, low power, ieee - 1284 compliant host - interfa ce parallel port, designed to interface to many peripherals such as printers, scanners and external drives. it supports compatibility modes, spp, nibble, ps2, epp and ecp modes. the register set is compatible with the microsoft register definition. the sy stem can access the parallel port via two blocks of i/o space; bar0 (8 bytes) contains the address of the basic parallel port registers, bar1 (4 bytes) contains the address of the upper registers. these are referred to as the ?lower block? and ?upper block ? in this section. if the upper block is located at an address 0x400 above the lower block, generic pc device drivers can be used to configure the port, as the addressable registers of legacy parallel ports always have this relationship. if not, a custom d river will be needed. 5.1.1 spp mode spp (output - only) is the standard implementation of a simple parallel port. in this mode, the pd lines always drive the value in the pdr register. all transfers are done under software control. input must be performed in nib ble mode. generic device driver - software may use the address in i/o space encoded in bar0 of function 1 to access the parallel port. the default configuration allocates 8 bytes to bar0 in i/o space. 5.1.2 ps2 mode this mode is also referred to as bi - direction al or compatible parallel port. in this mode, directional control of the pd lines is possible by setting & clearing dcr[5]. otherwise operation is similar to spp mode. 5.1.3 epp mode to use the enhanced parallel port ?epp? the mode bits (ecr[7:5]) must be set t o ?100?. the epp address and data port registers are compatible with the ieee 1284 definition. a write or read to one of the epp port registers is passed through the parallel port to access the external peripheral. in epp mode, the stb#, init#, afd# and sl in# pins change from open - drain outputs to active push - pull (totem pole) drivers (as required by ieee 1284) and the pins ack#, afd#, busy, slin# and stb# are redefined as intr#, datastb#, wait#, addrstb# and write# respectively. an epp port access begins with the host reading or writing to one of the epp port registers. the device automatically buffers the data between the i/o registers and the parallel port depending on whether it is a read or a write cycle. when the peripheral is ready to complete the tr ansfer it takes the wait# status line high. this allows the host to complete the epp cycle. if a faulty or disconnected peripheral failed to respond to an epp cycle the host would never see a rising edge on wait#, and subsequently lock up. a built - in time - out facility is provided in order to prevent this from happening. it uses an internal timer which aborts the epp cycle and sets a flag in the psr register to indicate the condition. when the parallel port is not in epp mode the timer is switched off to re duce current consumption. the host time - out period is 10 m s as specified with the ieee - 1284 specification. the register set is compatible with the microsoft register definition. assuming that the upper block is located 400h above the lower block, the regi sters are found at offset 000 - 007h and 400 - 402h. 5.1.4 ecp mode the extended capabilities port ?ecp? mode is entered when ecr[7:5] is set to ?011?. ecp mode is compatible with microsoft register definition of ecp, and ieee - 1284 bus protocol and timing. this implementation of the ecp port supports the optional decompression of received compressed data, but does not compress transmit data. assuming that the upper block is located 400h above the lower block, the registers are found at offset 000 - 007h and 400 - 4 02h. 5.2 parallel port interrupt the parallel port interrupt is asserted on inta#. it is enabled by setting dcr[4]. when dcr[4] is set, an interrupt is asserted on the rising edge of the ack# (intr#) pin and held until the status register is read, which reset s the int# status bit (dsr[2]).
data sheet revision 1.2 page 19 OX12PCI840 oxford semiconductor ltd. 5.3 register description the parallel port registers are described below. (nb it is assumed that the upper block is placed 400h above the lower block). register name address offset r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 spp (compatibility mode) registers pdr 000h r/w parallel port data register ecpafifo 000h r/w ecp fifo : address / rle dsr (epp mode) 001h r nbusy ack# pe slct err# int# 1 timeout (other modes) 001h r nbusy ack# pe slct err# int# 1 1 dc r 002h r/w 0 0 dir int_en nslin# init# nafd# nstb# eppa 1 003h r/w epp address register eppd1 1 004h r/w epp data 1 register eppd2 1 005h r/w epp data 2 register eppd3 1 006h r/w epp data 3 register eppd4 1 007h r/w epp data 4 register ecpdfifo 400h r/w ecp data fifo tfifo 400h r/w test fifo cnfga 400h r configuration a register ? always 90h cnfgb 401h r 0 int ?000000? ecr 402h r/w mode[2:0] must write ?00001? - 403h - reserved table 6 : parallel port register set note 1 : these registers are only available in epp mode. note 2 : prefix ?n? denotes that a signal is inverted at the connector. suffix ?#? denotes active - low signalling the reset state of pdr, eppa and eppd1 - 4 is not determinable (i.e. 0xxx). the reset value o f dsr is ?xxxxx111?. dcr and ecr are reset to ?0000xxxx? and ?00000001? respectively. 5.3.1 parallel port data register ?pdr? pdr is located at offset 000h in the lower block. it is the standard parallel port data register. writing to this register in mode 000 will drive data onto the parallel port data lines. in all other modes the drivers may be tri - stated by setting the direction bit in the dcr. reads from this register return the value on the data lines. 5.3.2 ecp fifo address / rle a data byte written to th is address will be interpreted as an address if bit(7) is set, otherwise an rle count for the next data byte. count = bit(6:0) + 1. 5.3.3 device status register ?dsr? dsr is located at offset 001h in the lower block. it is a read only register showing the current state of control signals from the peripheral. additionally in epp mode, bit 0 is set to ?1? when an operation times out (see section 5.1.3 ) dsr[0]: epp mode: timeout logic 0 t timeout has not occurred. logic 1 t timeout has occurred (reading this bit clears it). other modes: unused this bit is permanently set to 1. dsr[1]: unused this bit is permanently set to 1.
data sheet revision 1.2 page 20 OX12PCI840 oxford semiconductor ltd. dsr[2]: int# logic 0 t a parallel port interrupt is pending. logic 1 t no parallel port interr upt is pending. this bit is activated (set low) on a rising edge of the ack# pin. it is de - activated (set high) after reading the dsr. dsr[3]: err# logic 0 t the err# input is low. logic 1 t the err# input is high. dsr[4]: slct logic 0 t the slct inp ut is low. logic 1 t the slct input is high. dsr[5]: pe logic 0 t the pe input is low. logic 1 t the pe input is high. dsr[6]: ack# logic 0 t the ack# input is low. logic 1 t the ack# input is high. dsr[7]: nbusy logic 0 t the busy input is high. logic 1 t the busy input is low. 5.3.4 device control register ?dcr? dcr is located at offset 002h in the lower block. it is a read - write register which controls the state of the peripheral inputs and enables the peripheral interrupt. when reading this registe r, bits 0 to 3 reflect the actual state of stb#, afd#, init# and slin# pins respectively. when in epp mode, the write#, datastb# and addrstb# pins are driven by the epp controller, although writes to this register will override the state of the respective lines. dcr[0]: nstb# logic 0 t set stb# output to high (inactive). logic 1 t set stb# output to low (active). during an epp address or data cycle the write# pin is driven by the epp controller, otherwise it is inactive. dcr[1]: nafd# logic 0 t set afd# output to high (inactive). logic 1 t set afd# output to low (active). during an epp address or data cycle the datastb# pin is driven by the epp controller, otherwise it is inactive. dcr[2]: init# logic 0 t set init# output to low (active). logic 1 t set init# output to high (inactive). dcr[3]: nslin# logic 0 t set slin# output to high (inactive). logic 1 t set slin# output to low (active). during an epp address or data cycle the addrstb# pin is driven by the epp controller, otherwise it is i nactive. dcr[4]: ack interrupt enable logic 0 t ack interrupt is disabled. logic 1 t ack interrupt is enabled. dcr[5]: dir logic 0 t pd port is output. logic 1 t pd port is input. this bit is overridden during an epp address or data cycle, when the direction of the port is controlled by the bus access (read/write) dcr[7:6]: reserved these bits are reserved and always set to ?00?. 5.3.5 epp address register ?eppa? eppa is located at offset 003h in lower block, and is only used in epp mode. a byte written to this register will be transferred to the peripheral as an epp address by the hardware. a read from this register will transfer an address from the peripheral under hardware control. 5.3.6 epp data registers ?eppd1 - 4? the eppd registers are located at offse t 004h - 007h of the lower block, and are only used in epp mode. data written or read from these registers is transferred to/from the peripheral under hardware control. 5.3.7 ecp data fifo hardware transfers data from this 16 bytes deep fifo to the peripheral wh en dcr(5) = ?0?. when dcr(5) = ?1? hardware transfers data from the peripheral to this fifo. 5.3.8 test fifo used by the software in conjunction with the full and empty flags to determine the depth of the fifo and interrupt levels. 5.3.9 configuration a register ecr [7:5] must be set to ?111? to access this register. interrupts generated will always be level, and the ecp port only supports an impid of ?001?.
data sheet revision 1.2 page 21 OX12PCI840 oxford semiconductor ltd. 5.3.10 configuration b register ecr[7:5] must be set to ?111? to access this register. read only, all bits will be se t to 0, except for bit[6] which will reflect the state of the interrupt. 5.3.11 extended control register ?ecr? the extended control register is located at offset 002h in upper block. it is used to configure the operation of the parallel port. ecr[4:0]: reserv ed - write these bits are reserved and must always be set to ?00001?. ecr[0]: empty - read when dcr[5} = ?0? logic 0 t fifo contains at least one byte logic 1 t fifo completely empty when dcr[5} = ?1? logic 0 t fifo contains at least one byte logic 1 t fifo contains less than one byte ecr[1]: full - read when dcr[5} = ?0? logic 0 t fifo has at least one free byte fifo completely full when dcr[5} = ?1? logic 0 t fifo has at least one free byte logic 1 t fifo full ecr[2]: serviceintr - read when dcr[5} = ?0? logic 1 t writeintrthreshold (8) free bytes or more in fifo when dcr[5} = ?1? logic 1 t readintrthreshold (8) bytes or more in fifo ecr[7:5]: mode ? read / write these bits define the operational mode of the parallel port. logic ?000? spp logic ?001? ps2 logic ?010? reserved logic ?011? ecr logic ?100? epp logic ?101? reserved logic ?110? test logic ?111? config
data sheet revision 1.2 page 22 OX12PCI840 oxford semiconductor ltd. 6 s erial eeprom 6.1 specification the OX12PCI840 can be configured using an optional serial electrically - erasable programmable read only memory (eeprom). if the eeprom is not present, the device will remain in its default configuration after reset. although this may be adequate for some applications, many will benefit from the degree of programmability afforded by this feature. t he eeprom also allows configuration accesses to the parallel port, which can be useful for default set ups. the eeprom interface is based on the 93c46/56 serial eeprom devices which have a proprietary serial interface known as microwire tm . the interface h as four pins which supply the memory device with a clock, a chip - select, and serial data input and output lines. in order to read from such a device, a controller has to output serially a read command and address, then input serially the data. the 93c46/56 and compatible devices have a 16 - bit data word format but differ in memory size (and number of address bits). the OX12PCI840 incorporates a controller module which reads data from the serial eeprom and writes data into the configuration register space. it performs this operation in a sequence which starts immediately after a pci bus reset and ends either when the controller finds no eeprom is present or when it reaches the end of its data. note: that any attempted pci access while data is being downloade d from the serial eeprom will result in a retry . the operation of this controller is described below. following device configuration, driver software can access the serial eeprom through four bits in the device - specific local configuration register lcc[2 7:24]. software can use this register to manipulate the device pins in order to read and modify the eeprom contents. note that 93c46 and 93c56 eeprom devices offer 128 and 256 bytes of programmable data respectively. a windows based utility to program t he eeprom is available. for further details please contact oxford semiconductor (see back cover). microwire tm is a trade mark of national semiconductor. for a description of microwire tm , please refer to national semiconductor data manuals. 6.2 eeprom data o rganisation the serial eeprom data is divided in five zones. the size of each zone is an exact multiple of 16 - bit words. zone0 is allocated to the header. a valid eeprom program must contain a header. the eeprom can be programmed from the pci bus. once the programming is complete, the device driver should either reset the pci bus or set lcc[29] to reload the OX12PCI840 registers from the serial eeprom. the general eeprom data structure is shown in table 7 . data zone size (words) description 0 one header 1 one or more local configuration registers 2 one to four identification registers 3 two or more pci configuration registers 4 multiples of 2 function access table 7 : eeprom data format 6.2.1 zone0: header the header identifies the eeprom program as valid. bits description 15:4 these bits should return 0x840 to identify a valid program. once the ox12c840 reads 0x840 from these bits, it sets lcc[28] to indicate that a valid eeprom program is present. 3 1 = zone1 (local configuration) exists 0 = zone1 does not exist 2 1 = zone2 (identification) exists 0 = zone2 does not exist 1 1 = zone3 (pci configuration) exists 0 = zone3 does not exist 0 1 = zone4 (function access) exists 0 = zone4 does not exist th e programming data for each zone follows the proceeding zone if it exists. for example a header value of 0x840f indicates that all zones exist and they follow one another in sequence, while 0x8405 indicates that only zones 2 and 4 exist where the header da ta is followed by zone2 words, and since zone3 is missing zone2 words are followed by zone4 words.
data sheet revision 1.2 page 23 OX12PCI840 oxford semiconductor ltd. 6.2.2 zone1: local configuration registers the zone1 region of eeprom contains the program value of the vendor - specific local configuration registers us ing one or more configuration words. registers are selected using a 7 - bit byte - offset field. this offset value is the offset from base address registers in i/o or memory space (see section 4.4 ). note: not all of the registers in the local configuration register set are writable by eeprom. if bit3 of the header is set, zone1 configuration words follow the header declaration. the format of configuration words for the local configuration registers in zone1 are described in table 8 . bits description 15 ?0? = there are no more configuration words to follow in zone1. move to the next available zone or end eeprom program if no more zones are enabled in the header. ?1? = there is another configuration word to follow for the local configuration registers. 14:8 these seven bits define the byte - offset of the local configuration register to be programmed. for example the byte - offset for lt2[23:16] is 0x0e. 7:0 8 - bit value of the register to be programmed table 8 : zone 1 data format 6.2.3 zone2: identification registers the zone2 region of eeprom contains the program value for vendor id and subsystem vendor id. the format of device identification configuration words are described in table 9 . bits description 15 ?0? = there are no more zone2 (identification) bytes to program. move to the next available zone or end eeprom program if no more zones are enabled in the header. ?1? = there is a nother zone2 (identification) byte to follow. 14:8 0x00 = vendor id bits [7:0]. 0x01 = vendor id bits [15:8]. 0x02 = subsystem vendor id [7:0]. 0x03 = subsystem vendor id [15:8]. 0x03 to 0x7f = reserved. 7:0 8 - bit value of the register to be programme d table 9 : zone 2 data format 6.2.4 zone3: pci configuration registers the zone3 region of eeprom contains any changes required to the pci configuration registers (with the exception of vendor id and subsystem vendor id whic h are programmed in zone2). this zone consists of a function header word, and one or more configuration words for that function. the function header is described in table 10 . bits description 15 ?0? = end of zone 3. ?1? = def ine this function header. 14:3 reserved. write zeros. 2:0 function number for the following configuration word(s). ?000? = function0 other values = reserved. table 10 : zone 3 data format (function header) the subsequent words for each function contain the address offset and a byte of programming data for the pci configuration space belonging to the function number selected by the proceeding function - header. the format of configuration words for the pci configuration registers a re described below.
data sheet revision 1.2 page 24 OX12PCI840 oxford semiconductor ltd. bits description 15 ?0? = this is the last configuration word in for the selected function in the function - header. ?1? = there is another word to follow for this function. 14:8 these seven bits define the byte - offset of the pci co nfiguration register to be programmed. for example the byte - offset of the interrupt pin register is 0x3d. offset values are tabulated in section 4.2 . 7:0 8 - bit value of the register to be programmed table 11 : zone 3 data format (data) table 12 shows which pci configuration registers are writable from the eeprom for each function. offset bits description 0x02 7:0 device id bits 7 to 0. 0x03 7:0 device id bits 15 to 8. 0x06 3:0 must be ?0000?. 0x06 4 extended capabilities. 0x06 7:5 must be ?000?. 0x09 7:0 class code bits 7 to 0. 0x0a 7:0 class code bits 15 to 8. 0x0b 7:0 class code bits 23 to 16. 0x2e 7:0 subsystem id bits 7 to 0. 0x2f 7:0 subsystem id bits 15 to 8. 0x3d 7:0 interrupt pin. 0x42 7:0 power management capabilities bits 7 to 0. 0x43 7:0 power management capabilities bits 15 to 8. table 12 : eeprom - writable pci configuration registers
data sheet revision 1.2 page 25 OX12PCI840 oxford semiconductor ltd. 6.2.5 zone4: function ac cess zone 4 allows the parallel port to be configured, prior to pci access. this can be useful for patching designs to work with generic drivers, enabling interrupts, etc. each 8 - bit (function) access is equivalent to accessing the function through i/o b ars 0 and 1, with the exception that a function read access does not return any data (discarded). each entry in zone 4 comprises 2 16 bit words. the format is as shown in table 14. 1 st word of function access pair word bits description 15 ?1? - anoth er word to follow 14:12 bar number to access 000 for bar 0 001 for bar 1 others reserved 11 ?0? : read access (data discarded) ?1? : write access 10:8 reserved ? write 0?s 7:0 i/o address to access this is the location (i/o offset from the relevant base address) that needs to be written/read. 2 nd word of function access pair word bits description 15 ?1? ? another function access word pair to follow. ?0? ? no more function access pairs. end eeprom program. 14:8 reserved ? write 0?s 7:0 data to be written to location. field unused for function access reads .
data sheet revision 1.2 page 26 OX12PCI840 oxford semiconductor ltd. 7 o perating c onditions symbol parameter min max units v dd dc supply voltage - 0.3 7.0 v v in dc input voltage - 0.3 v dd + 0.3 v i in dc input current +/ - 10 ma t s tg storage temperature - 40 125 c table 13 : absolute maximum ratings symbol parameter min max units v dd dc supply voltage 4.5 5.5 v t c temperature 0 70 c table 14 : recommended operating conditions 8 dc e lectrical c haracteristics 8.1 non - pci i/o buffers symbol parameter condition min max units v dd supply voltage commercial 4.75 5.25 v v ih input high voltage ttl interface 1 ttl schmitt trig 2.0 2.0 v v il input low voltage ttl interface 1 ttl schmitt trig 0.8 0.8 v c il cap of input buffers 5.0 pf c ol cap of output buffers 10.0 pf i ih input high leakage current v in = v dd - 10 10 m a i il input low leakage current v in = v ss - 10 10 m a v oh output high voltag e i oh = 1 m a v dd ? 0.05 v v oh output high voltage i oh = 4 ma 2 2.4 v v ol output low voltage i ol = 1 m a 0.05 v v ol output low voltage i ol = 4 ma 2 0.4 v i oz 3 - state output leakage current - 10 10 m a symbol parameter typical max units operating supply current in normal mode tbd tbd i cc operating supply current in power - down mode tbd ma table 15 : characteristics of non - pci i/o buffers note 1: al l input buffers are ttl with the exception of pci buffers note 2: i oh and i ol are 12 ma for pd/lbdb[7:0] and other parallel port outputs. they are 4 ma for all other non - pci outputs
data sheet revision 1.2 page 27 OX12PCI840 oxford semiconductor ltd. 8.2 pci i/o buffers symbol parameter condition min max unit dc specificati ons v cc supply voltage 4.75 5.25 v v il input low voltage - 0.5 0.8 v v ih input high voltage 2.0 v cc + 0.5 v i il input low leakage current v in = 0.5v - 70 m a i ih input high leakage current v in = 2.7v 70 m a v ol output low voltage i out = - 2 ma 0.55 v v oh output low voltage i out = 3 ma, 6ma 2.4 v c in input pin capacitance 10 pf c clk clk pin capacitance 5 12 pf c idsel idsel pin capacitance 8 pf l pin pin inductance 10 nh ac specifications switching current 0 < v out 1.4 - 44 i oh(ac) high 1.4 < v out 2.4 - 44 (v out - 1.4)/0.024 ma 3.1 < v out v cc eq. a (test point) v out = 3.1 - 142 switching current v out 2.2 95 i ol(ac) low 2.2 > v out > 0.55 v out / 0.023 ma 0.71 > v out > 0 eq. b (test point ) v out = 0.71 206 i cl low clamp current - 5 < v in < - 1 - 25 + (v in +1)/ 0.015 ma i hl high clamp current v cc +4 < v in < v cc +1 25+ (v in - v cc - 1)/ 0.015 ma slew r output rise slew rate 0.4v to 2.4v 1 5 v/ns slew f output fall slew rate 2.4v to 0.4v 1 5 v/n s table 16 : characteristics of pci i/o buffers eq. a : i oh = 11.9 * (v out - 5.25) * (v out + 2.45) for 3.1 < v out v cc eq. b : i ol = 78.5 * v out * (4.4 - v out ) for 0.71 > v out > 0
data sheet revision 1.2 page 28 OX12PCI840 oxford semiconductor ltd. 9 ac e lectrical c haracteristics 9.1 pci bus the timings for pci pins comply with pci specification for the 5.0 volt signalling environment.
data sheet revision 1.2 page 29 OX12PCI840 oxford semiconductor ltd. 10 t iming w aveforms clk frame# ad[31:0] c/be[3:0]# irdy# trdy# devsel# stop# address bus cmd byte enable# 1 2 3 4 data data transfer figure 1 : pci read transaction from local configuration registers clk frame# ad[31:0] c/be[3:0]# irdy# trdy# devsel# stop# address bus cmd byte enable# 1 2 3 4 data data transfer figure 2 : pci write transaction to local configuration registers
data sheet revision 1.2 page 30 OX12PCI840 oxford semiconductor ltd. 11 p ackage d etails
data sheet revision 1.2 page 31 OX12PCI840 oxford semiconductor ltd. 12 n otes this page has been intentionally left blank
data sheet revision 1.2 page 32 OX12PCI840 oxford semiconductor ltd. 13 c ontact d etails oxford semiconductor ltd. 25 milton park abingdon oxfordshire ox14 4sh united kingdom telephone: +44 (0)1235 824900 fax: +44 (0)1235 821141 sales e - mail: sales@oxsemi.com tech support e - mail: support@o xsemi.com web site: http://www.oxsemi.com d isclaimer oxford semiconductor believes the information contained in this document to be accurate and reliable. however, it is subject to change without notice. no responsibilit y is assumed by oxford semiconductor for its use, nor for infringement of patents or other rights of third parties. no part of this publication may be reproduced, or transmitted in any form or by any means without the prior consent of oxford semiconductor ltd. oxford semiconductor?s terms and conditions of sale apply at all times.

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